CompuLab Trim-Slice Uživatelský manuál Strana 1

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Strany 1 - Trim-Slice

Trim-Slice Reference Guide

Strany 2

Interfaces and Connectors Revised July 2011 Trim-Slice 10 3.2 System Memory 3.2.1 DRAM The Trim-Slice features 1 GB of DDR2. The DRAM i

Strany 3 - Table of Contents

Interfaces and Connectors Revised July 2011 Trim-Slice 11 3.4 Audio Subsystem 3.4.1 Analog Audio The Trim-Slice analog audio subsys

Strany 4 - Table of Contents

Interfaces and Connectors Revised July 2011 Trim-Slice 12 3.4.2 S/PDIF The S/PDIF output is implemented with the Tegra2 S/PDIF interface

Strany 5

Interfaces and Connectors Revised July 2011 Trim-Slice 13 3.7 SATA Controller The Trim-Slice SATA functionality is implemented with the

Strany 6 - 1 INTRODUCTION

Interfaces and Connectors Revised July 2011 Trim-Slice 14 4 SYSTEM LOGIC 4.1 Power Subsystem 4.1.1 Power Rails The Trim-Slice is power

Strany 7 - 2 OVERVIEW

Interfaces and Connectors Revised July 2011 Trim-Slice 15 4.3 Real Time Clock The Trim-Slice RTC is implemented with the EM Microelectro

Strany 8 - 2.3 Features

Interfaces and Connectors Revised July 2011 Trim-Slice 16 5 INTERFACES AND CONNECTORS 5.1 HDMI Connector (J1) The primary HDMI display

Strany 9 - 3 CORE SYSTEM COMPONENTS

Interfaces and Connectors Revised July 2011 Trim-Slice 17 5.3 DC Power Jack (J3) DC power input connector. Table 12 J3 connector pi

Strany 10 - 3.3 Display Subsystem

Interfaces and Connectors Revised July 2011 Trim-Slice 18 5.6 RS232 connector (P3) The Trim-Slice RS232 port is routed to the on-board R

Strany 11 - 3.4.1 Analog Audio

Interfaces and Connectors Revised July 2011 Trim-Slice 19 5.8 USB Host Connectors (P6, P8, P9, P11) The Trim-Slice external USB2.0 h

Strany 12 - 3.5.3 USB-2

Revised July 2011 Trim-Slice 2 © 2011 CompuLab No warranty of accuracy is given concerning the contents of the information contained in this

Strany 13

Interfaces and Connectors Revised July 2011 Trim-Slice 20 5.10 USB Device Connector (P10) The Tegra2 USB-1 port is routed through the US

Strany 14 - 4 SYSTEM LOGIC

Interfaces and Connectors Revised July 2011 Trim-Slice 21 5.12 Extension Connector (P19) NOTE: JTAG signals operate at 1.8V voltage leve

Strany 15 - 4.3 Real Time Clock

Interfaces and Connectors Revised July 2011 Trim-Slice 22 5.14 Power Button (SW1) The Trim-Slice power button SW1 controls the system po

Strany 16 - 5 INTERFACES AND CONNECTORS

Mechanical Drawings Revised July 2011 Trim-Slice 23 6 MECHANICAL DRAWINGS The mechanical drawings below are provided for connector locat

Strany 17 - 5.5 SD Socket (P2)

Operational Characteristics Revised July 2011 Trim-Slice 24 7 OPERATIONAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Table 33 A

Strany 18 - 5.7 Audio Jacks (P4, P5)

Table of Contents Revised July 2011 Trim-Slice 3 Table of Contents 1 INTRODUCTION ...

Strany 19

Table of Contents Revised July 2011 Trim-Slice 4 5.1 HDMI Connector (J1) ...

Strany 20 - 5.11 SATA Connector (P18)

Revised July 2011 Trim-Slice 5 Table 1 Document Revision Notes Date Description May 2011  First release July 2011  Added power mo

Strany 21

Revised July 2011 Trim-Slice 6 1 INTRODUCTION 1.1 About This Document This document is part of a set of reference documents providing

Strany 22 - 5.16 Indicator LEDs

Revised July 2011 Trim-Slice 7 2 OVERVIEW 2.1 Highlights The Trim-Slice is a fully functional miniature computer based on the NVIDIA

Strany 23 - 6 MECHANICAL DRAWINGS

Revised July 2011 Trim-Slice 8 2.3 Features Table 3 CPU, Graphics and Memory Feature Specifications Notes CPU NVIDIA Tegra2 dual-core

Strany 24

Interfaces and Connectors Revised July 2011 Trim-Slice 9 3 CORE SYSTEM COMPONENTS 3.1 Tegra 250 SoC 3.1.1 Dual-Core ARM Cortex-A9 CPU

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